A CPU contains many important components: registers, an ALU, control logic, memory interfaces, and other supporting circuits.
But these components are useful only when they work together.
One of the most important connections inside a processor is the path between the register file and the Arithmetic Logic Unit, or ALU.
The register file stores values that the CPU is actively using.
The ALU performs arithmetic and logical operations on those values.
So a fundamental CPU data path looks like this:
Register File
↓
ALU
↓
Register File
This article follows one simple MIPS instruction through that path:
add $t0, $t1, $t2
The instruction means:
$t0 = $t1 + $t2
It looks simple in assembly language.
But inside the processor, several hardware components must cooperate to make it happen.
1. Start with the ADD Instruction
Consider this MIPS instruction:
add $t0, $t1, $t2
There are three registers involved.
$t1 is the first source register.
$t2 is the second source register.
$t0 is the destination register.
Conceptually:
$t1 + $t2 → $t0
Suppose:
$t1 = 25
and:
$t2 = 17
The processor must calculate:
25 + 17 = 42
and place the result into:
$t0
From the programmer’s perspective, that is the entire operation.
Inside the CPU, however, the process is much more interesting.
2. The CPU Needs Two Source Operands
An addition requires two input values.
The ALU therefore needs to receive:
Operand A
and:
Operand B
For our instruction:
add $t0, $t1, $t2
the two operands come from:
$t1
and:
$t2
This is one reason the MIPS register file normally provides two read ports.
It allows two registers to be read at the same time.
Conceptually:
$t1 → Read Data 1
$t2 → Read Data 2
These two values can then feed the ALU simultaneously.
3. The Register File Does Not Read Register Names
Assembly language uses names such as:
$t0
$t1
$t2
But the hardware does not understand those names.
MIPS registers are identified by register numbers.
In the traditional MIPS naming convention:
$t0 = register 8
$t1 = register 9
$t2 = register 10
So:
add $t0, $t1, $t2
ultimately tells the hardware to use register numbers:
8, 9, 10
Because a classic MIPS register file contains 32 registers, identifying one register requires:
5 bits
since:
2^5 = 32
These 5-bit register numbers are encoded directly inside the instruction.
4. The Instruction Contains the Register Addresses
A classic MIPS R-type instruction is 32 bits long.
Its major fields include:
Opcode
rs
rt
rd
shamt
funct
For an ADD instruction:
rs
identifies the first source register.
rt
identifies the second source register.
rd
identifies the destination register.
For:
add $t0, $t1, $t2
the mapping is:
rs = $t1
rt = $t2
rd = $t0
The CPU therefore gets the register addresses directly from the instruction bits.
The instruction itself tells the register file which values to read and where the result should eventually be written.
5. Two Register Addresses Enter the Register File
The register file receives two read addresses.
The first address comes from:
rs
The second address comes from:
rt
For our example:
rs → $t1
rt → $t2
Inside the register file, these addresses select two stored 32-bit values.
Conceptually:
Read Register 1 → $t1
Read Register 2 → $t2
The outputs become:
Read Data 1
and:
Read Data 2
The important point is that both values are available at the same time.
6. Why the Register File Has Two Read Ports
Suppose the processor had only one read port.
To execute:
$t0 = $t1 + $t2
it might need to read $t1 first and then read $t2.
That would complicate instruction execution.
Instead, a typical MIPS register file allows two independent register reads.
The data path becomes:
$t1 → Read Data 1
$t2 → Read Data 2
at essentially the same stage of instruction execution.
This structure matches the needs of instructions such as:
ADD
SUB
AND
OR
SLT
because these operations normally use two register operands.
The architecture of the register file and the structure of the instruction set are closely related.
7. The Register File Feeds the ALU
Now we reach the critical connection.
The two outputs from the register file travel toward the ALU.
Conceptually:
Register File
Read Data 1 → ALU Input A
Read Data 2 → ALU Input B
For:
add $t0, $t1, $t2
this becomes:
$t1 → ALU Input A
$t2 → ALU Input B
If:
$t1 = 25
and:
$t2 = 17
then the ALU receives:
Input A = 25
Input B = 17
The ALU now has the data it needs.
But it still needs to know what operation to perform.
8. The ALU Does More Than Addition
An ALU is not just an adder.
Depending on the processor design, the ALU may perform operations such as:
Addition
Subtraction
AND
OR
XOR
Comparison
Shift-related operations may also be handled by the ALU or by separate hardware, depending on the implementation.
So simply sending $t1 and $t2 into the ALU is not enough.
The processor must also tell the ALU:
What operation should you perform?
That requires control signals.
9. The Control Unit Decodes the Instruction
The processor examines the instruction bits to determine what kind of instruction is being executed.
For a classic MIPS R-type ADD instruction, the main opcode indicates an R-type instruction.
Additional function bits specify the exact operation.
The control logic interprets these fields.
For an ADD instruction, it ultimately generates an ALU control signal telling the ALU to perform:
ADD
Conceptually:
Instruction
↓
Control Logic
↓
ALU Control = ADD
↓
ALU
At the same time, the register file has already supplied the two operands.
Now the ALU knows both:
the data
and:
the operation.
10. The ALU Performs the Addition
The ALU receives:
Input A = value from $t1
Input B = value from $t2
ALU Control = ADD
Using our example:
Input A = 25
Input B = 17
The arithmetic circuitry inside the ALU produces:
ALU Result = 42
At the hardware level, this addition may ultimately be implemented using networks of full adders or more advanced adder structures.
The ALU therefore connects the logic-gate level of the processor to the instruction level seen by software.
At the bottom:
logic gates build adders.
Adders become part of the ALU.
The ALU executes the arithmetic requested by machine instructions.
11. The ALU Result Is Not Finished Yet
After the ALU calculates:
25 + 17 = 42
the processor still has one more major job.
The result must be stored somewhere.
For:
add $t0, $t1, $t2
the destination is:
$t0
So the value:
42
must travel from the ALU back to the register file.
This path is commonly called part of the:
write-back path
Conceptually:
Register File
↓
ALU
↓
ALU Result
↓
Write Back
↓
Register File
The register file is therefore both a source of operands and a destination for results.
12. The Destination Register Comes from rd
The processor already knows where the result must go.
The destination register number is encoded in the instruction.
For an R-type ADD instruction, that destination comes from:
rd
For:
add $t0, $t1, $t2
the destination is:
$t0
which is register:
8
So the register file receives:
Write Register = 8
Write Data = 42
But simply placing these signals at the register file does not necessarily change the register immediately.
A write-enable signal is also required.
13. RegWrite Enables the Register Update
The register file must not write a value during every instruction.
Some instructions modify registers.
Others do not.
For example:
ADD writes a register.
SUB writes a register.
LW writes a register.
SW does not write a general-purpose register.
A branch instruction normally does not write a general-purpose register.
Therefore, the control unit generates a signal commonly called:
RegWrite
For an ADD instruction:
RegWrite = 1
This tells the register file:
Store the incoming result in the selected destination register.
Conceptually:
Write Register = $t0
Write Data = ALU Result
RegWrite = 1
Now the hardware is prepared to update $t0.
14. Register Reads and Writes Behave Differently
A classic register file is often designed so that reads are combinational while writes are clocked.
That distinction is important.
When the read register addresses change, the corresponding register values can propagate toward the read outputs without waiting for another clock edge.
The write operation is different.
The destination register is typically updated on an active clock edge.
So during the instruction:
add $t0, $t1, $t2
the processor can read:
$t1
and:
$t2
use those values in the ALU,
and then update:
$t0
at the appropriate clock-controlled point.
This combination of combinational data flow and clocked storage is fundamental to synchronous processor design.
15. The Complete ADD Data Path
We can now put the pieces together.
Start with:
add $t0, $t1, $t2
The instruction identifies:
Source 1 = $t1
Source 2 = $t2
Destination = $t0
The full data flow is:
Instruction
↓
Extract rs, rt, rd
↓
Register File
↓
Read $t1 and $t2
↓
Read Data 1 and Read Data 2
↓
ALU
↓
ADD
↓
ALU Result
↓
Write Data
↓
Register File
↓
Write $t0
Using actual values:
$t1 = 25
$t2 = 17
The flow becomes:
25
plus:
17
enter the ALU.
The ALU produces:
42
The processor then writes:
42
into:
$t0
The instruction is complete.
16. This Is a Data Path
The connections we have been following are part of what computer architecture calls the:
datapath
The datapath contains the hardware structures through which values move and are transformed.
Typical datapath components include:
Register File
ALU
Multiplexers
Program Counter
Adders
Immediate-generation hardware
Memory interfaces
The control unit determines how these components should behave for each instruction.
A useful way to think about the processor is:
The datapath moves and transforms data.
The control unit tells the datapath what to do.
This distinction becomes extremely important when studying CPU architecture.
17. Why Multiplexers Soon Become Necessary
Our ADD example is intentionally simple.
Both ALU operands come directly from registers.
But not every instruction works that way.
Consider an instruction that adds an immediate constant.
One ALU input may come from a register, while the other must come from an immediate value encoded in the instruction.
That creates a choice:
Register value
or:
Immediate value
A multiplexer can select which value reaches the ALU.
Likewise, different instructions may choose different destination registers or different sources for write-back data.
As the processor supports more instruction types, multiplexers become essential for building a flexible datapath.
This is where a simple register-file-to-ALU connection begins to grow into a complete CPU datapath.
18. ADD and LW Use the ALU Differently
The ALU is not used only for arithmetic instructions.
Consider:
lw $t0, 8($t1)
The processor must calculate a memory address:
address = $t1 + 8
The ALU performs that addition.
But the second ALU input is no longer another register value.
Instead, it is an immediate offset.
So:
ADD instruction:
Register + Register → ALU
LW instruction:
Register + Immediate → ALU
This explains why a multiplexer is often placed before one of the ALU inputs.
It allows the processor to select the correct source depending on the instruction.
19. SW Also Uses the Register File and ALU
Consider:
sw $t0, 8($t1)
This instruction needs two different register values for two different purposes.
$t1
provides the base address.
$t0
provides the data that will be written to memory.
The ALU calculates:
$t1 + 8
to produce the memory address.
Meanwhile, the value from $t0 travels toward the memory write-data input.
This demonstrates an important idea:
The two outputs of the register file do not always serve exactly the same purpose.
Their roles depend on the current instruction.
The control system determines how the datapath is used.
20. The Register File Is at the Center of CPU Execution
The register file occupies an important position inside the processor.
Many instructions begin by reading one or more registers.
The values then travel to components such as:
the ALU
memory-address generation logic
comparison logic
or other execution units.
After execution, many results return to the register file.
So instruction execution often follows a pattern like:
Read operands
↓
Execute operation
↓
Write result
Or more specifically:
Register File
↓
Execution Unit
↓
Register File
This pattern appears throughout processor architectures, not only in MIPS.
21. From Register File to ALU to CPU
Previously, we could study the register file as an independent hardware block.
That teaches us how a processor can store and access a small number of extremely important working values.
But the register file becomes much more meaningful when connected to the ALU.
Now we can see a larger structure emerging:
Registers store operands.
The register file supplies operands.
The ALU performs operations.
The result returns through the write-back path.
Control signals coordinate the entire process.
Together, these components form the foundation of CPU instruction execution.
22. From Logic Gates to an ADD Instruction
This also reveals an important chain of abstraction.
At the lowest level:
Transistors
form:
Logic Gates
Logic gates form:
Adders
Adders become part of:
The ALU
The ALU receives data from:
The Register File
The register file and ALU together execute operations requested by:
Machine Instructions
And those machine instructions ultimately implement:
Programs
So a simple line of assembly language such as:
add $t0, $t1, $t2
connects software all the way down to digital logic.
That is one of the most important ideas in computer architecture.
23. What Happens Next?
We have now connected two major CPU components:
The Register File
and:
The ALU
But we still have only part of the processor.
A complete CPU must also answer questions such as:
How is an instruction fetched?
How does the processor know which instruction comes next?
Where does the Program Counter fit into the datapath?
How do load and store instructions communicate with memory?
How does a branch change control flow?
How does the control unit select the correct paths?
Once these components are connected, we move from individual circuits toward a complete processor datapath.
Conclusion
A MIPS instruction such as:
add $t0, $t1, $t2
looks simple in assembly language.
But inside the processor, it activates an organized hardware data flow.
The instruction identifies two source registers:
$t1
and:
$t2
The register file reads both values simultaneously.
Those values travel into the two ALU inputs.
Control logic tells the ALU to perform addition.
The ALU produces the result.
That result travels through the write-back path.
Finally, the register file stores the result in:
$t0
So the essential flow is:
Instruction
↓
Register File
↓
ALU
↓
Write Back
↓
Register File
This is more than a connection between two CPU components.
It is the beginning of the CPU datapath.
Once we understand this path, we can begin following an entire machine instruction through the processor—from instruction fetch, through register access and execution, all the way to the final result.
And that is where individual digital circuits start becoming a working CPU.