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Category: Risc-V

RISC-V is a modern, open instruction set architecture designed for clarity, flexibility, and long-term scalability.

Unlike closed architectures, RISC-V gives engineers full control — from instruction design to CPU implementation.

This makes it ideal for:

  • Custom silicon and SoC design
  • FPGA-based CPU development
  • Operating system research
  • Hardware/software co-design

In this category, you won’t just learn theory — you’ll learn how to build real CPUs.

Why Linux and RISC-V Are a Perfect Match

Introduction Over the past thirty years, Linux has changed the software world. It powers most web servers, cloud platforms, supercomputers, networking devices, and countless embedded…

RV32I register files

Registers and Core Concepts

================================================== 1. Registers Registers are tiny, very fast storage locations inside the CPU. RV32I has 32 integer registers: Each register is 32 bits wide. You…

RV32I FPGA Implementation Roadmap

Here’s a practical, no-fluff RV32I FPGA implementation roadmap — focused on getting you from zero → running code on hardware. hase 0 — Setup (1…

RISC-V Pseudo-Instruction Lookup Table

RISC-V Pseudo-Instruction Lookup Table Assembler Pseudo-instructions The assembler implements a number of convenience psuedo-instructions that are formed from instructions in the base ISA, but have…