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Learning Verilog and FPGA Tutorial From Beginning

Posted in FPGA and Verilog
FPGA and Verilog
FPGA and Verilog

Verilog Introduction
Verilog Modules and ports
Comment Statement and File Header Writing
Verilog Module Instantiation and Simple Hierarchical Circuit Design.

The use of bidirectional ports in FPGA and Verilog implementation.
Verilog syntax for module instantiation
Module statement programming and experimentation.

Verilog Identifiers and Data Types
Verilog Identifiers and Keywords
Verilog Bit Data and Number Representation
Verilog Variable Declaration and Basic Data Types 1 (wire, reg)
Verilog Variable Declaration and Extended Data Types 2
Verilog Variable Declaration and Data Types 3 (Variable Vector Field Selection)
Verilog Precompilation (Macros, Parameters, …)

Verilog Operators
Classification of Verilog Operators
Logical Operators and Expressions
Relational Operators and Expressions
Equality Operators and Expressions
Bitwise Operators and Expressions
Arithmetic Operators and Expressions
Shift Operators and Expressions
Bit Concatenation Operators and Expressions
Reduction Operators and Expressions
Operator Precedence
Differences between ‘not’, ‘!’, and ‘~’ in Verilog
Usage of ‘X’ for signals or values in Verilog


Verilog Syntax Practice

Verilog Syntax Practice (1) Simple Combinational Logic
Verilog Syntax Practice (2) Vector
Verilog Syntax Practice (3) Module Instantiation
Verilog Syntax Practice (4) Combinational Logic, Avoiding Latch Generation
Verilog Syntax Practice (5) BCD Adder
Verilog Syntax Practice (6) Flip-Flop Model
Verilog Syntax Practice (7) Counter, Arithmetic Right Shift, LFSR Implementation
Verilog Syntax Practice (8) State Machine
Verilog Syntax Practice (9) Advanced State Machine
Verilog Syntax Practice (10) Designing Complex Counters
Verilog Syntax Practice (11) Implementing Circuits through Waveforms
Verilog Odd and Even Divider Logic


Verilog Expressions and Statements

Concurrent Assignment Statements and Concurrent Processes
Sequential Statements
always blocks
Function Calls – function
Application of Verilog Function in PRBS
Verilog Tasks – Syntax and Usage
Computing Fibonacci Series using Verilog Task

Related:   What is The Difference Between Verilog and Verilog HDL ?

Conditional Statements
if statement
case statement
ternary operator “?”

Looping Statements
for loop statement
Verilog forever loop statement
while loop statement
Verilog repeat loop statement

Blocking and Non-blocking Assignment Statements in Verilog
Differences between Blocking and Non-Blocking Assignment Statements in Verilog

In-depth Discussion of Variable Types and Usage Range in Verilog
Generate Statements in Verilog

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