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Learning Risc-V From Beginning

Posted in Risc-V

1.RISC-V Introduction

the Origin of RISC-V, and the Features of RISC-V
RISC-V Instruction Set Architecture Features and Classification
RISC-V Instruction Set Encoding Structure, Features and Advantages

2.RISC-V Instruction Set Explanation and Assembly Language Programming

RISC-V Instruction Set Explanation (1) : General Purpose Registers and Assembly Instruction Classification
RISC-V Instruction Set Explanation (2): I-Type integer register-immediate instructions
RISC-V Instruction Set Explanation (3): I-Type Shift Instructions
RISC-V Instruction Set Explanation (4): U-Type Integer Register-Immediate Instructions. 
RISC-V Instruction Set Explanation (5): R-Type integer register-register instructions
RISC-V Instruction Set Explanation (6) – Conditional and Unconditional Jump Instructions
RISC-V Instruction Set Explanation (7) Load/store instructions
RISC-V Instruction Explanation (8) – Instruction Address Alignment and Addition/Subtraction Overflow Handling

RISC-V Pseudo-Instruction Lookup Table

3. RISC-V Assembly Language Programming 

RISC-V asm_compile Tool Usage
RISC-V Assembly Language Programming (1) Running Light Design
RISC-V Assembly Language Programming (2) Assembly Program asm_run_led
RISC-V Assembly Language Programming (3) Compilation Environment and Board Experiment
RISC-V Assembly Language Programming (4) Assembly Language Format and ABI
FII-PRX100-D Development Board FPGA Burning and RISC-V Software Code Download

RISC-V CSR Register
RISC-V CSR Register (1) Introduction to CSR and CSR Instructions
RISC-V CSR Register (2) CSR Registers

RISC-V CPU hardware design (IP core)

This is a list of topics related to the hardware design of a RISC-V CPU IP core:

RISC-V 32 Registers and Decoding Module
RISC-V 32 Registers and Decoding Module (1): Classic 5-stage pipeline of the CPU
RISC-V 32 Registers and Decoding Module (2): CPU hardware module
RISC-V 32 Registers and Decoding Module (3): Register file
RISC-V 32 Registers and Decoding Module (4): Instruction decoder
RISC-V ALU Module and Branch
RISC-V ALU Module and Branch (1): ALU module
RISC-V ALU Module and Branch (2): Branch module
RISC-V CSR Read/Write Control
RISC-V CSR Read/Write Control (1): exu_csr module
RISC-V CSR Read/Write Control (2): csr_reg module
RISC-V CSR Read/Write Control (3): Implementation of CSR registers (part 1)
RISC-V CSR Read/Write Control (4): Implementation of CSR registers (part 2)
RISC-V CSR Read/Write Control (5): Implementation of CSR registers (part 3)
RISC-V LSU, SRAM, GPIO Module
RISC-V LSU, SRAM, GPIO Module (1): exu_lsu module
RISC-V LSU, SRAM, GPIO Module (2): D_sram module
RISC-V LSU, SRAM, GPIO Module (3): fii_GPIO module
RISC-V EXU Module and CPU Operation
RISC-V EXU Module and CPU Operation (1): rv32i_exu module
RISC-V EXU Module and CPU Operation (2): CPU operation process (based on pipeline)
RISC-V Timer and Interrupt
RISC-V Timer and Interrupt (1): Reading and writing timer interrupt registers
RISC-V Timer and Interrupt (2): Generating timer interrupts
Simulation Techniques for RISC-V IP Core
Using $readmemh in Vivado simulation project
Loading block memory files in Vivado simulation project
Common Issues and Solutions in RISC-V Hardware Design
Common issues and solutions in RISC-V hardware design (part 1)
Common issues and solutions in RISC-V hardware design (part 2)
Common issues and solutions in RISC-V hardware design (part 3)

Related:   RISC-V Instruction Set Explanation (6) - Load/Store Instructions

Software development and application for RISC-V CPU.

RISC-V Software IDE Development Environment and Usage (1) Freedom Studio Installation and Interface
RISC-V Software IDE Development Environment and Usage (2) Creating a New Experiment Project
RISC-V Software IDE Development Environment and Usage (3) Project Download
RISC-V Software IDE Development Environment and Usage (4) Debugging the run_led Project
RISC-V Software IDE Development Environment and Usage (5) Debugging the run_seg Project
RISC-V C Language Programming 1
RISC-V C Language Programming 1 (1) FII-RISC-V CPU Introduction and C Language Compilation Process
RISC-V C Language Programming 1 (2) Creating a C Language Project
RISC-V C Language Programming 1 (3) Linker Script
RISC-V C Language Programming 2
RISC-V C Language Programming 2 (1) Display Project for 7-Segment Display
RISC-V C Language Programming 2 (2) Button Project
RISC-V C Language Programming 2 (3) Interrupt and Interrupt Project
RISC-V Experimental Course – Introduction to Button and 7-Segment Display Series

 

RISC-V CPU System-on-Chip design

RISC-V Bus and Pipeline

RISC-V Bus and Pipeline (1) Introduction to Bus
RISC-V Bus and Pipeline (2) RISC-V CPU Bus Design
RISC-V Bus and Pipeline (3) Introduction to Pipeline
RISC-V Bus and Pipeline (4) Introduction to RISC-V CPU Pipeline
RISC-V PLIC (Platform-Level Interrupt Controller) Design

Introduction to RISC-V PLIC
RISC-V PLIC Design (1) CPU Design
RISC-V PLIC Design (2) Software Design – Top
RISC-V PLIC Design (3) Software Design – Bottom
RISC-V GPIO Interrupt Design and Application

RISC-V GPIO Interrupt Design and Application (1)
RISC-V GPIO Interrupt Design and Application (2)
RISC-V PWM Interrupt Design and Application

RISC-V PWM Interrupt Design and Application (1) Introduction and Design of PWM
RISC-V PWM Interrupt Design and Application (2) PWM Engineering Code and Example Waveform
RISC-V UART Interrupt Design and Application

Related:   R-Type Integer Register-Register Instructions - RISC-V Instruction Set Explanation (4)

RISC-V UART Interrupt Design and Application (1) Introduction and Design of UART
RISC-V UART Interrupt Design and Application (2) Implementation of UART1 CPU and Engineering Header Files
RISC-V UART Interrupt Design and Application (3) Main Function of Software Engineering
RISC-V I2C Interrupt Design and Application

RISC-V I2C Interrupt Design and Application (1) Introduction and Design of I2C
RISC-V I2C Interrupt Design and Application (2) Implementation of I2C0 Module CPU and Engineering Header Files
RISC-V I2C Interrupt Design and Application (3) Main Function of Software Engineering
RISC-V Digital Tube IP Design and Application

7-segment digital tube IP CPU interface encapsulation
RISC-V Ethernet Design and Application

Ethernet module reference
Ethernet module (IP core) RISCV interface encapsulation
Mathematical IP Core Design

FPGA floating-point arithmetic algorithm
Floating-point arithmetic calculation method (addition and subtraction)
Floating-point arithmetic calculation method (multiplication and division)
CPU Cache Design Origin

 

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