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Verilog Comment Statement and File Header Writing

Posted in FPGA and Verilog

Verilog is a hardware description language that is commonly used in the design of digital circuits. When working with Verilog code, it is important to include header files and comment sentences in order to make the code more readable and understandable for other engineers who may be working on the project.

Header files in Verilog typically include information about the module or design unit that the code is describing. This information may include the name of the module, the author of the code, and the date that the code was last modified. Including this information in the header file can help to identify the purpose of the code and ensure that it is properly attributed to its original author.

Comment sentences are also an important aspect of Verilog code. Comments are used to describe the purpose and functionality of the code, as well as to provide information about any assumptions or limitations that may be relevant to the code. Comments can be used to explain complex logic or algorithms, and can also be used to provide context for future engineers who may need to modify or extend the code.

When writing comment sentences in Verilog, it is important to use a consistent format and to be clear and concise in the description of the code. Comments should be placed at the beginning of each module or design unit, as well as at the beginning of any significant blocks of code within the module. This can help to ensure that the purpose and functionality of the code is clear to anyone who reads it.

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In addition to header files and comment sentences, it is also important to organize Verilog code in a clear and logical manner. This can be achieved by using descriptive module and signal names, as well as by using hierarchical design techniques to break the code down into smaller, more manageable components.

Overall, the use of header files and comment sentences is an important aspect of writing clear and understandable Verilog code. By providing clear and concise documentation of the purpose and functionality of the code, engineers can ensure that their code is properly understood and maintained by others who may be working on the project.

Verilog Comment Statement and File Header Writing Example

Verilog syntax and C language have many similarities, especially in the way comment sentences are written.

There are two types of comments available:

  • line comments //
  • block comments /* … */


Comments are not considered part of the code and only serve to provide annotations to improve the readability of the program. The compiler automatically ignores comments during compilation.

Line comment sentences // comments only one line, from // to the end of the line. Line comments are often used to explain the meaning, intent, and tips of the line of code, or to comment out a line of code.

Example 1. An example of a Verilog module with a header file and line comment sentences:

// File: adder.v
// Author: John Smith
// Date: 4/12/2023

module adder (
  input [3:0] a,
  input [3:0] b,
  output [3:0] sum

  // This module implements a 4-bit adder
  // The inputs are two 4-bit numbers (a and b)
  // The output is the sum of the two numbers (sum)

  assign sum = a + b;


In this example, the header file at the top of the file includes information about the module and its author and date. The comment sentences within the module provide additional information about the purpose and functionality of the code.

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The module itself is a simple 4-bit adder, which takes two 4-bit inputs (a and b) and produces a 4-bit output (sum). The assign statement performs the addition operation and assigns the result to the sum output.

By including a header file and comment sentences, this code is much more readable and understandable for other engineers who may be working on the project. The header file provides important information about the code, while the comment sentences provide context and explanation for the functionality of the code.

Example 2. An example of block comments comment sentences:

`timescale 1ns/1ps

module tb

reg [3:0] a, b, c;

wire [3:0] d;
wire [3:0] e;

    a = 'b0;
    b = 'b0;
    c = 'b0;

    a = 'd7;
    b = 'd9;
    c = 'd12;

    a = 'b11x1;


cmp cmp_dut
    .a (a),
    .b (b),
    .c (c),
    .d (d),
    .e (e)




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