RISC-V is an open-source instruction set architecture (ISA) that was originally developed at the University of California, Berkeley in 2010. The project was led by Krste Asanović, Andrew Waterman, and David Patterson, who sought to create an ISA that was both free and open, allowing for innovation and experimentation in computer architecture.

The RISC-V ISA is based on the principles of Reduced Instruction Set Computing (RISC), which advocates for a simpler, more streamlined instruction set that can be executed more quickly and efficiently than complex instruction sets. The RISC-V design is modular and extensible, allowing designers to choose which instructions to include in their implementations and to create custom instructions for specialized tasks.

Since its inception, RISC-V has gained popularity in both industry and academia due to its open-source nature, flexibility, and potential for innovation. It is used in a variety of applications, including microcontrollers, embedded systems, and high-performance computing.

1. Instruction Set Architecture

Instruction Set Architecture (ISA) is an abstract model that includes the instruction set, registers, memory handling, addressing modes, interrupt and exception handling, and external I/0 interfaces. The instruction set consists of a set of opcodes, or machine codes, and basic commands executed by a particular processor. ISA specifies the behavior of machine codes running on its implementation in a way that is not dependent on its implementation characteristics. The central processing unit (CPU) can be seen as an implementation of ISA.

ISA can be classified in many different ways, the most widespread classification is based on the complexity of its architecture, which can be divided into complex instruction set computer (CISC) and reduced instruction set computer (RISC). Well-known CISC microprocessors/controllers include Motorola (Motorola) 6800, Intel (Intel) 8080 and X86 series. RISC-based architectures include ARM, RISC-V, MIPS, etc.

CISC is characterized by its emphasis on hardware, including some complex instructions with multiple clock cycles, prone to semantic gaps, and small code size, while RISC is characterized by its bias toward software, simple architecture, including only single-clock-cycle condensed instructions, and large code size.

In summary, CISC reduces the number of instructions at the expense of clock cycles consumed per instruction, while RISC greatly reduces the cycles per instruction at the cost of multiple instruction counts. the RISC strategy brings some very important advantages in that single-clock-cycle instructions require less transistor hardware space compared to CISC, thus leaving more space for general-purpose registers.

However, the extent of ISA diffusion depends not only on architectural excellence but also on commercialization, and although RISC has many advantages, RISC chip development is lagging behind CISC due to the lack of software support. Without commercial interest, many developer companies are also unable to mass produce RISC chips, thus lowering their prices and making them more competitive.

2. the Origin of the RISC-V Instruction Set

The RISC-V architecture was invented in 2010 by Professor Krste Asanovic, Andrew Waterman and Yunsup Lee at the University of California, Berkeley, with the help and support of Turing Award winner Professor David Patterson. The University of California, Berkeley is known as the “cradle of electrical engineers” and is a world leader in many aspects of electrical engineering research. At the time, Professor Krste Asanovic was teaching a class on CPU architecture and was torn between X86 and ARM, hoping for a better choice to achieve better teaching results. However, after an in-depth study of the CPUs already on the market, he decided to lead the development of a new architecture himself. In contrast to other ISAs, RISC-V does not require any person or company to pay royalties for designing, producing and selling chips with the RISC-V architecture. It has now reached its fifth generation, hence the name RISC-V (V-five), which can also be interpreted as Vector due to the release of a draft version of the vector instructions during the same period.

In May 2017, RISC-V released version 2.22 of the instruction set in user space (user space ISA), while the privileged instruction set (privileged ISA) was also in draft version 1.10. On December 13, 2019, it was updated with the unprivileged instruction set version 2.2 (i.e., the earlier user space instruction set), the privileged instruction set version 1.11 , and debug instruction set version 0.13.2. These three versions are the latest versions available.

3. Why is RISC-V Launched?

As mentioned above, the CISC-based X86 series and the RISC-based ARM series were commercially mature and widespread, and the market for CPUs was basically monopolized by ARM and Intel, with ARM having been developed in 1985 and Intel X86 having been introduced in 1978. It seemed that RISC-V had basically no chance to develop, yet eventually RISC-V was promoted for the following reasons:

• The X86 and ARM architectures became extremely complex and redundant in order to be backward compatible. After decades of development, the original architecture was modified and expanded several times to accommodate new needs that emerged, which added significant costs for learning, use, and maintenance.
• The development and production of X86/ARM chips requires high patent and licensing fees, which are very unfriendly to startups. Royalty Fee).
• X86 and ARM are non-open source systems, RTL code is not available or can not be modified. For example, the X86 assembly language classes in colleges and universities, usually only software teaching, can not actually practice to modify its hardware to deepen understanding, its meaning is not significant; ARM currently has two licensing methods, one is the architecture license, the other is the “ARM processor IP” license (about millions of dollars).

4. the Features of RISC-V

RISC-V has two main features:

• RISC-V ISA is completely open source, and it can be freely used for any purpose, allowing anyone to design, manufacture, and sell the associated chips and software. This feature is the primary reason why the RISC-V ISA appears in many US university lecture materials.
• It has no backward-compatible baggage and overcomes many of the shortcomings of existing CPU ISA architectures, giving it a real backward advantage.

Among the many RISC ISA CPUs, RISC-V stands out because most RISC CPU designers focus more on IP CORE and hardware system design than on ecosystem creation. The RISC-V Foundation is composed of Google, IBM, Microchip and other companies, and its headquarters has been moved from the United States to Switzerland.