Detailed Beginner Guide to RV32I: The Base Integer Instruction Set of RISC-V

RV32I is the mandatory base 32-bit integer instruction set in the RISC-V architecture. It contains approximately 47 instructions and forms the foundation for every RISC-V processor.

Its design is simple, regular, and highly suitable for FPGA implementation.

Want to build your own RISC-V CPU from scratch on an FPGA?

Start here with RV32I — the foundational 32-bit integer instruction set of RISC-V.

Simple. Clean. Perfect for learning.

Here’s everything you need to know in one thread:

1/6 pic.twitter.com/lrCYA9Jmtp

— IC and CS Tutorial (@riscvprogram) April 1, 2026

1. The Register File (32 Registers)

RV32I provides 32 general-purpose 32-bit registers labeled x0 to x31.

• x0 (also called zero) is hardwired to 0 and cannot be written.
• The remaining 31 registers are fully general-purpose.

Compilers and assemblers use standard ABI names (Application Binary Interface):

• x0 = zero — always zero
• x1 = ra — return address
• x2 = sp — stack pointer
• x3 = gp — global pointer
• x4 = tp — thread pointer
• x5–x7 = t0–t2 — temporary registers
• x8–x9 = s0–s1 — saved registers
• x10–x17 = a0–a7 — function arguments and return values
• x18–x27 = s2–s11 — saved registers
• x28–x31 = t3–t6 — temporary registers

Tip: Always prefer ABI names when writing assembly (e.g., addi a0, zero, 42).

2. RV32I Instruction Formats

Every RV32I instruction is exactly 32 bits long. There are six main formats:

3. RV32I Instructions Overview

Arithmetic & Logical (Register-Register)

• add rd, rs1, rs2 — rd = rs1 + rs2
• sub rd, rs1, rs2 — rd = rs1 – rs2
• and, or, xor
• sll, srl, sra — logical/arithmetic shifts

Arithmetic & Logical with Immediate

• addi rd, rs1, imm — most frequently used instruction
• andi, ori, xori
• slli, srli, srai

Compare and Set

• slt / slti — set less than (signed)
• sltu / sltiu — set less than unsigned

Load and Store

Branches (B-type)

• beq, bne
• blt, bge (signed)
• bltu, bgeu (unsigned)

Jumps

• jal rd, imm — jump and link
• jalr rd, rs1, imm — jump and link register

Upper Immediate

• lui rd, imm — load upper immediate
• auipc rd, imm — add upper immediate to PC

System Instructions

• ecall, ebreak -(environment call / break)


4. How to Build These in Your FPGA CPU (Single-Cycle View)

In a basic single-cycle RISC-V CPU on FPGA, you need these major components:

In a basic single-cycle RISC-V CPU you implement:

1. Instruction Fetch → PC → Instruction Memory
2. Decode → extract rs1, rs2, rd, opcode, funct3, funct7, immediate
3. Register File → read rs1/rs2
4. Immediate Generator → create correct 32-bit immediate based on format
5. ALU → perform add/sub/logic/shift/compare
6. Data Memory → for loads/stores
7. Writeback → write result back to rd
8. Next PC logic → for branches/jumps

Here are visual examples of the single-cycle datapath:

This shows the complete data flow of a basic RV32I CPU (Program Counter, Instruction Memory, Register File, Immediate Generator, ALU, Data Memory, Control Unit, etc.).

5. Implementation Tips for FPGA

1. Start by implementing the ALU (add/sub/logic/shifts/slt).
2. Build the Immediate Generator (different wiring for each instruction format).
3. Create the Register File.
4. Implement the Control Unit (combinational logic based on opcode + funct3 + funct7).
5. Test each instruction thoroughly in simulation before synthesizing.

Bruno Levy’s learn-fpga tutorial adds instructions gradually — highly recommended for beginners.

6. Configurable RV32I RTL Processor Microarchitecture Diagram

A detailed block-level view focusing on pipeline stages, ALU, register file, hazard detection, and memory interfaces — excellent reference for building on FPGA.

Ready to Code?

Next logical steps:

1. Implement and test addi and add.
2. Add load/store instructions.
3. Implement branches and jumps.