Introduction
An interrupt is a hardware or software mechanism that allows a processor to respond to an event requiring attention.
Instead of continuously checking whether a device needs service, the CPU can be notified when an important event occurs.
Interrupts are fundamental to modern computing. They are used in operating systems, microcontrollers, embedded systems, networking equipment, and real-time applications.
For example, when a keyboard key is pressed, a network packet arrives, or a hardware timer expires, an interrupt may notify the processor that an event needs to be handled.
Interrupts allow computers to respond efficiently to external and internal events while continuing to perform other tasks.
How Does an Interrupt Work?
A processor normally executes instructions according to the program’s control flow.
When an interrupt is accepted, the CPU temporarily redirects execution to a special routine called an Interrupt Service Routine (ISR), or interrupt handler.
A simplified interrupt process works as follows.
1. Event Occurs: A hardware device or internal processor component generates an interrupt request.
2. Interrupt Recognition: The processor or interrupt controller determines whether the interrupt is enabled and eligible for servicing.
3. Save Processor State: The processor saves the information required to resume interrupted execution. Depending on the architecture, additional registers may be saved by software.
4. Execute Interrupt Handler: The CPU transfers control to the appropriate ISR, which responds to the event.
5. Return from Interrupt: After processing, the handler restores the required state and executes a special interrupt-return instruction.
6. Resume Execution: The processor resumes the interrupted program or another task selected by the operating system.
The exact procedure depends on the CPU architecture and operating system.
Main Types of Interrupts
Interrupts can be classified according to their sources and behavior.
Hardware Interrupts
Hardware interrupts originate from physical devices or hardware components.
Common examples include keyboard events, network interface notifications, timer expiration, and completion of data transfers.
For example, a network interface controller may generate an interrupt after receiving data, allowing the operating system to process the incoming information.
Hardware interrupts are usually delivered through interrupt controllers or processor-specific interrupt mechanisms.
Software Interrupts
Software interrupts are triggered by executing specific instructions or using software-defined mechanisms.
Historically, software interrupts have been used to request operating system services.
For example, x86 systems support the INT instruction, which can invoke a software interrupt or trap.
Modern operating systems frequently use specialized system-call instructions instead of traditional software interrupts for ordinary system calls.
Exceptions
Exceptions occur when the processor detects a condition during instruction execution.
Examples include division by zero, invalid instructions, page faults, and certain memory-access violations.
Exceptions are closely related to interrupts because they also redirect execution to specialized handlers.
However, exceptions are generally associated with the current instruction, while external hardware interrupts are usually asynchronous events.
Maskable vs. Non-Maskable Interrupts
Interrupts can also be classified by whether normal interrupt-masking mechanisms can disable them.
Maskable Interrupts: These interrupts can be enabled, disabled, or temporarily blocked through processor or interrupt-controller mechanisms.
They are commonly used for ordinary hardware events such as timers, communication interfaces, and peripheral devices.
Non-Maskable Interrupts (NMI): These are high-priority interrupt mechanisms that cannot be blocked by ordinary interrupt masking.
NMIs are often associated with critical hardware conditions, watchdog mechanisms, or system diagnostics.
However, NMI behavior and available sources vary by processor architecture.
What Is an Interrupt Service Routine?
An Interrupt Service Routine is a special function or routine executed in response to an interrupt.
Its purpose is to handle the event that caused the interrupt.
For example, when a UART peripheral receives data, its interrupt handler may read a received byte, update a buffer, and acknowledge the interrupt condition.
Interrupt handlers should generally complete their immediate work quickly.
Long-running interrupt handlers can delay other interrupts and increase system response times.
Operating systems often divide interrupt processing into immediate handling and deferred work.
In Linux, mechanisms such as threaded interrupts, softirqs, and workqueues can help move suitable processing outside the most time-critical interrupt context.
What Is an Interrupt Vector Table?
An interrupt vector table is a structure that helps the processor identify the correct handler for a particular interrupt or exception.
Each interrupt source or exception type is associated with a handler address or an entry used to locate the handler.
For example, Arm Cortex-M processors use an exception vector table containing the initial stack pointer value and handler addresses.
In x86 systems, the Interrupt Descriptor Table (IDT) contains descriptors used to locate interrupt and exception handlers.
When an interrupt is accepted, the processor uses the relevant architectural mechanism to transfer execution to the appropriate handler.
The details differ significantly between processor families.
What Is an Interrupt Controller?
An interrupt controller manages interrupt requests from hardware devices and coordinates their delivery to the processor.
Its responsibilities may include interrupt prioritization, masking, routing, and handling multiple simultaneous requests.
Common examples include:
PIC (Programmable Interrupt Controller): A traditional interrupt controller used in older PC architectures.
APIC (Advanced Programmable Interrupt Controller): An interrupt-controller architecture used in x86 multiprocessor systems. Modern systems may also support interrupt remapping and other advanced mechanisms.
NVIC (Nested Vectored Interrupt Controller): Integrated into Arm Cortex-M processors, supporting interrupt priorities, nesting, and efficient exception handling.
PLIC (Platform-Level Interrupt Controller): A controller used in some RISC-V systems for managing external interrupt sources.
Modern RISC-V systems may also use newer interrupt architectures, including Advanced Interrupt Architecture (AIA) components.
Interrupt controllers are especially important in systems containing many peripherals or processor cores.
Interrupt Priority and Nested Interrupts
Some interrupts require faster handling than others.
For example, a time-sensitive motor-control event may have higher priority than an ordinary communication notification.
Interrupt controllers and processor hardware may support priority levels to determine which events receive attention first.
In systems supporting nested interrupts, a higher-priority interrupt can interrupt the execution of a lower-priority interrupt handler.
This improves responsiveness for critical events but introduces additional complexity.
Software must carefully manage shared data, synchronization, and interrupt priorities to avoid race conditions and unpredictable behavior.
Interrupts vs. Polling
Interrupts and polling are two common approaches to detecting hardware events.
Polling: The CPU repeatedly checks a device’s status to determine whether an event has occurred.
Interrupts: The device or hardware subsystem notifies the CPU when an event needs attention.
Polling is simple and can provide predictable behavior in certain applications. However, frequent polling may waste CPU cycles when events occur infrequently.
Interrupts allow the processor to perform other work until an event occurs, improving efficiency in many systems.
Nevertheless, interrupts also introduce processing overhead.
For high-speed networking and other workloads with frequent events, a combination of interrupts and polling can provide better performance than either method alone.
Interrupts and DMA
Direct Memory Access (DMA) and interrupts often work together.
DMA allows hardware controllers to transfer data between peripherals and memory without requiring the CPU to handle every byte.
After a DMA transfer completes, the controller may generate an interrupt to notify the processor.
For example, a microcontroller can configure DMA to collect ADC samples into RAM.
When the configured buffer is filled, a DMA completion interrupt informs the CPU that the data is ready for processing.
This approach reduces repetitive CPU work and supports efficient real-time data acquisition.
High-performance systems may use similar mechanisms for network packets, storage operations, and other data transfers.
Interrupt Latency and Real-Time Systems
Interrupt latency is the time between an interrupt event becoming eligible for service and the processor beginning the appropriate handling.
Low interrupt latency is important in real-time systems such as industrial controllers, robotics, automotive electronics, and embedded communication devices.
Several factors affect interrupt latency.
Interrupt Masking: Temporarily disabled interrupts may delay event processing.
Interrupt Priority: Higher-priority requests may be serviced before lower-priority ones.
Processor Architecture: Exception-entry mechanisms, pipeline behavior, and register-saving requirements affect response time.
Operating System Activity: Critical sections, scheduling mechanisms, and interrupt-handling policies can introduce delays.
Cache and Memory Effects: Instruction and data access delays may increase interrupt response time.
Real-time systems are often designed to provide bounded and predictable interrupt response behavior rather than simply maximizing average processing speed.
Interrupts in Different Processor Architectures
Different CPU architectures implement interrupts using different hardware mechanisms.
x86-64: Uses interrupt and exception handling through mechanisms such as the IDT, APIC architecture, and specialized processor instructions.
Arm Cortex-M: Provides integrated exception handling through the NVIC, with configurable priorities and support for nested interrupts.
RISC-V: Defines architectural trap and interrupt mechanisms using control and status registers such as mtvec, mstatus, and mcause. Platform-level interrupt delivery depends on the implementation.
Microcontrollers: Commonly provide interrupts for GPIO events, timers, ADCs, UART, SPI, I²C, and other peripherals.
Multicore Processors: May use interprocessor interrupts (IPIs) to coordinate activities between CPU cores.
Although implementation details vary, the common purpose is to redirect processor execution when important events require handling.
Why Are Interrupts Important?
Interrupts improve the responsiveness and efficiency of modern computing systems.
They allow operating systems to handle device events without continuously polling every peripheral.
They support multitasking by enabling timer-driven scheduling and asynchronous I/O.
In embedded systems, interrupts allow processors to react to sensor inputs, communication events, and time-sensitive control conditions.
Interrupts also help coordinate DMA transfers, hardware error reporting, and communication between processor cores.
However, excessive interrupt activity can reduce performance, making interrupt moderation, prioritization, and efficient handler design important.
Conclusion
An interrupt is a mechanism that allows a processor to temporarily redirect execution in response to hardware events, software requests, or exceptional conditions.
Interrupt controllers, interrupt vector tables, and Interrupt Service Routines work together to identify and handle these events.
Interrupts are essential for operating systems, microcontrollers, embedded devices, networking equipment, and real-time applications.
Understanding interrupts provides an important foundation for studying CPU architecture, operating systems, device drivers, DMA, embedded Linux, RISC-V processors, and real-time computing.